1. Field of the Invention
The present invention relates to a digital time base corrector for use in an apparatus for reproducing a video signal recorded on a recording medium.
2. Description of Background Information
When a video signal recorded on a video disk is merely demodulated and reproduced, a reproduced video signal may include fine jitter due to eccentric components of the video disc and vibrations caused in the mechanical system of the apparatus, resulting in a time base error which represents a deviation of the reproduction video signal from a reference time base. For correcting the time base error, a digital time base corrector known in which the reproduction video signal is converted to the digital data by an A/D converter, subsequently the digital data is written into a memory and is read out in accordance with the writing order synchronously with a reference timing signal, and the read out data is reconverted to an analog signal by a D/A converter.
A conventional digital time base corrector is, for example, disclosed in Japanese Patent Application Kokai No. 1-93273. In this time base corrector, a phase locked loop (PLL) circuit in which at least one of a horizontal sync signal and a color burst signal is separated and extracted from the reproduction video signal and to which the separation signal is supplied is provided. The PLL circuit generates a clock signal whose phase is synchronized with the time base error included in the reproduction video signal. The clock signal is phase modulated by phase modulating means in accordance with a phase comparison output of phase comparing means in the PLL circuit. The clock signal after completion of the phase modulation is used as a sample timing signal of the A/D converter. The clock signal, consequently, traces even a high frequency component of the time base error, thereby performing the correction.
According to such a digital time base corrector, it is desirable to reduce a memory capacity of a memory to a value of about 1H (H: horizontal scan period) of the video signal in order to realize the low costs. Although read addresses are ordinarily changed in such a way as to follow write addresses which are sequentially designated to write the video signal in the memory, however, in the case where a period of clock signal is largely fluctuated by a jitter included in the demodulated video signal, the writing operation to the memory is delayed and the reading operation which is performed at a predetermined period is advanced from the writing operation with respect to the addresses. When such a situation occurs, since the video signal of 1H before is read out, in case of the video signal of the NTSC system, a condition such that the phase of a color signal is inverted by 180.degree. every 1H is not maintained, so that an interleave relation between a luminance signal and the color signal of the video signal cannot be held.